1. Field of the Invention
The present invention generally relates to the field of electronic logic circuits and, more particularly, to integrated circuits, such as Application-Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) and system-on-chip systems. More specifically the present invention relates to a method for analyzing a logic circuit comprising a number of components and channels for exchange of data between components, where each component and each channel is assigned functional properties in a circuit model to simulate a way in which the logic circuit functions.
2. Description of the Related Art
Logic circuits are used in numerous electrical and electronic devices or systems. Such circuits generally comprise a substrate (e.g., a semiconductor substrate) on which different circuit elements or circuit element blocks are accommodated and wired to one another. These circuit elements or circuit element blocks are also referred to as components. An integrated circuit usually consists of a number of different components, which are accommodated on a monocrystalline substrate. If all or a large part of the desired functions are implemented on one chip, this is referred to as a system-on-chip. By means of this integration, comprehensive functionalities and applications are available in the very smallest space. The rapid progress in technological development means that the possibility currently exists to accommodate complex logic circuits with a large number of components on a single semiconductor chip.
Such complex circuits are usually designed via computer-based aids. In such cases, a virtual circuit model is first created in order to simulate a desired way of functioning. In concrete terms each component (hardware components; system components that consist of hardware and software portions, etc.) is represented by a functional component model, in order to construct a circuit model of the logic circuit or of the logical system therefrom. Based on this circuit model, a functionality of the corresponding circuit is able to be checked and verified via simulation. This applies especially for a circuit model with a high degree of abstraction, which is also referred to as a high-level model. Using a high-level programming language such as C++, SystemC or System Verilog, the functional component models and circuit models of logic circuits can be captured, represented and a functional behavior of the logic circuit as well as the individual components of the logic circuit can be simulated. More specifically, in this case, e.g., runtimes and performance of the individual functional components are defined as parameters, so that the circuit model behaves during a simulation like the corresponding real circuit or behaves like a real hardware model.
An important aim in the development of complex circuits (systems) is protecting them from attacks (security attacks). In order to render such attacks more difficult or to avoid them, security measures are integrated into the design of the circuit. With these measures, security-relevant data stored or processed in the system is to be protected. In order to determine these security measures and lay them out in an optimal way, an analysis of the design is required. In this analysis, an investigation is performed to determine which components of the system can be affected explicitly or implicitly by attacks and which security measures are sensible to a given extent for a respective use case.
Usually, such an analysis occurs based on ongoing inspection and reviews of the system by a developer (architects) during a development process. The use of an “attack-tree” analysis is also known.
Because of the increasing size and complexity of logic circuits it is becoming increasingly difficult to investigate comprehensively the effects of possible attacks on the functionality and security of the circuits.